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| 1 219543f ltc2195 ltc2194/ltc2193 applications n communications n cellular base stations n software-defned radios n portable medical imaging n multi-channel data acquisition n nondestructive testing typical application description 16-bit, 125/105/80msps low power dual adcs the ltc ? 2195/ltc2194/ltc2193 are 2-channel, simul - taneous sampling 16-bit a/d converters designed for digitizing high frequency, wide dynamic range signals. they are perfect for demanding communications applica - tions with ac performance that includes 76.8db snr and 90db spurious free dynamic range (sfdr). ultralow jitter of 0.07ps rms allows undersampling of if frequencies with excellent noise performance. dc specs include 2lsb inl (typ), 0.5lsb dnl (typ) and no missing codes over temperature. the transition noise is 3.4lsb rms . to minimize the number of data lines the digital outputs are serial lvds. each channel outputs two bits or four bits at a time. at lower sampling rates there is a one bit per channel option. the lvds drivers have optional internal termination and adjustable output levels to ensure clean signal integrity. the enc + and enc C inputs may be driven differentially or single ended with a sine wave, pecl, lvds, ttl or cmos inputs. an internal clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. features n 2-channel simultaneous sampling adc n serial lvds outputs: 1, 2 or 4 bits per channel n 76.8db snr n 90db sfdr n low power: 432mw/360mw/249mw total n 216mw/180mw/125mw per channel n single 1.8v supply n selectable input ranges: 1v p-p to 2v p-p n 550mhz full-power bandwidth s/h n shutdown and nap modes n serial spi port for confguration n 52-pin (7mm 8mm) qfn package 2-tone fft, f in = 70mhz and 69mhz 16-bit adc core ch1 analog input ch2 analog input encode input s/h 16-bit adc core out1a out1b out1c out1d out2a out2b out2c out2d data clock out frame s/h data serializer pll ognd 219543 ta01a serialized lvds outputs gnd v dd ov dd 1.8v 1.8v l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 60 219543 ta01b
ltc2195 ltc2194/ltc2193 2 219543f supply voltages v dd , ov dd ................................................ C0.3v to 2v analog input voltage a in +, a in C, par/ ser, sense (note 3) .................................... C0.3v to (v dd + 0.2v) digital input voltage enc + , enc C , cs, sdi, sck (note 4) ...... C0.3v to 3.9v sdo (note 4) ............................................ C0.3v to 3.9v digital output voltage ................ C0.3v to (ov dd + 0.3v) operating temperature range ltc2195c, ltc2194c, ltc2193c ............. 0c to 70c ltc2195i, ltc2194i, ltc2193i ............ C40c to 85c storage temperature range ................... C65c to 150c (notes 1, 2) 16 15 17 18 19 top view 53 gnd ukg package 52-lead (7mm 8mm) plastic qfn 20 21 22 23 24 25 26 51 52 50 49 48 47 46 45 44 43 42 41 33 34 35 36 37 38 39 40 8 7 6 5 4 3 2 1v cm1 gnd a in1 + a in1 ? gnd refh refl refh refl par/ser a in2 + a in2 ? gnd v cm2 out1c + out1c ? out1d + out1d ? dco + dco ? ov dd ognd fr + fr? out2a + out2a ? out2b + out2b ? v dd v dd sense gnd v ref gnd sdo gnd out1a + out1a ? out1b + out1b ? v dd v dd enc + enc ? cs sck sdi gnd out2d ? out2d + out2c ? out2c + 32 31 30 29 28 27 9 10 11 12 13 14 t jmax = 150c, ja = 28c/w exposed pad (pin 53) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range ltc2195cukg#pbf ltc2195cukg#trpbf ltc2195ukg 52-lead (7mm 8mm) plastic qfn 0c to 70c ltc2195iukg#pbf ltc2195iukg#trpbf ltc2195ukg 52-lead (7mm 8mm) plastic qfn C40c to 85c ltc2194cukg#pbf ltc2194cukg#trpbf ltc2194ukg 52-lead (7mm 8mm) plastic qfn 0c to 70c ltc2194iukg#pbf ltc2194iukg#trpbf ltc2194ukg 52-lead (7mm 8mm) plastic qfn C40c to 85c ltc2193cukg#pbf ltc2193cukg#trpbf ltc2193ukg 52-lead (7mm 8mm) plastic qfn 0c to 70c ltc2193iukg#pbf ltc2193iukg#trpbf ltc2193ukg 52-lead (7mm 8mm) plastic qfn C40c to 85c consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container. consult ltc marketing for information on non-standard lead based fnish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/ pin configuration absolute maximum ratings 3 219543f ltc2195 ltc2194/ltc2193 converter characteristics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 5) parameter conditions ltc2195 ltc2194 ltc2193 units min typ max min typ max min typ max resolution (no missing codes) l 16 16 16 bits integral linearity error differential analog input (note 6) l C7 2 7 C7.5 2 7.5 C7.5 2 7.5 lsb differential linearity error differential analog input l C0.9 0.5 0.9 C0.9 0.5 0.9 C0.9 0.5 0.9 lsb offset error (note 7) l C7 1.5 7 C7 1.5 7 C7 1.5 7 mv gain error internal reference external reference l C2.0 1.5 C0.7 0.6 C1.8 1.5 C0.5 0.8 C1.8 1.5 C0.5 0.8 %fs %fs offset drift 10 10 10 v/c full-scale drift internal reference external reference 30 10 30 10 30 10 ppm/c ppm/c gain matching 0.3 0.3 0.3 %fs offset matching 1.5 1.5 1.5 mv transition noise 3.4 3.5 3.2 lsb rms analog input the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 5) symbol parameter conditions min typ max units v in analog input range (a in + C a in C) 1.7v < v dd < 1.9v l 1 to 2 v p-p v in(cm) analog input common mode (a in + + a in C)/2 differential analog input (note 8) l 0.7 v cm 1.25 v v sense external voltage reference applied to sense external reference mode l 0.625 1.250 1.300 v i incm analog input common mode current per pin, 125msps per pin, 105msps per pin, 80msps 200 170 130 a a a i in1 analog input leakage current (no encode) 0 < a in +, a in C < v dd l C1 1 a i in2 par/ ser input leakage current 0 < par/ ser < v dd l C3 3 a i in3 sense input leakage current 0.625v < sense < 1.3v l C6 6 a t ap sample-and-hold acquisition delay time 0 ns t jitter sample-and-hold acquisition delay jitter single-ended encode differential encode 0.07 0.09 ps rms ps rms cmrr analog input common mode rejection ratio 80 db bwC3b full-power bandwidth figure 6 test circuit 550 mhz ltc2195 ltc2194/ltc2193 4 219543f dynamic accuracy the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. a in = C1dbfs. (note 5) symbol parameter conditions ltc2195 ltc2194 ltc2193 units min typ max min typ max min typ max snr signal-to-noise ratio 5mhz input 70mhz input 140mhz input l 74.5 76.8 76.6 76.1 74.8 76.7 76.5 76 75.1 77.1 76.9 76.4 dbfs dbfs dbfs sfdr spurious free dynamic range 2nd harmonic 5mhz input 70mhz input 140mhz input l 79 90 89 84 81 90 89 84 81 90 89 84 dbfs dbfs dbfs spurious free dynamic range 3rd harmonic 5mhz input 70mhz input 140mhz input l 81 90 89 84 81 90 89 84 82 90 89 84 dbfs dbfs dbfs spurious free dynamic range 4th harmonic or higher 5mhz input 70mhz input 140mhz input l 88 95 95 95 89 95 95 95 89 95 95 95 dbfs dbfs dbfs s/(n+d) signal-to-noise plus distortion ratio 5mhz input 70mhz input 140mhz input l 73.3 76.6 76.2 75.1 74 76.5 76.1 75 74.4 76.9 76.5 75.3 dbfs dbfs dbfs crosstalk 10mhz input C110 C110 C110 dbc internal reference characteristics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 5) parameter conditions min typ max units v cm output voltage i out = 0 0.5 ? v dd C 25mv 0.5 ? v dd 0.5 ? v dd + 25mv v v cm output temperature drift 25 ppm/c v cm output resistance C600a < i out < 1ma 4 v ref output voltage i out = 0 1.225 1.250 1.275 v v ref output temperature drift 25 ppm/c v ref output resistance C400a < i out < 1ma 7 v ref line regulation 1.7v < v dd < 1.9v 0.6 mv/v digital inputs and outputs the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 5) symbol parameter conditions min typ max units encode inputs (enc + , enc C ) differential encode mode (enc C not tied to gnd) v id differential input voltage (note 8) l 0.2 v v icm common mode input voltage internally set externally set (note 8) l 1.1 1.2 1.6 v v v in input voltage range enc + , enc C to gnd (note 8) l 0.2 3.6 v r in input resistance see figure 10 10 k c in input capacitance (note 8) 3.5 pf 5 219543f ltc2195 ltc2194/ltc2193 digital inputs and outputs the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 5) symbol parameter conditions min typ max units single-ended encode mode (enc C tied to gnd) v ih high level input voltage v dd =1.8v l 1.2 v v il low level input voltage v dd =1.8v l 0.6 v v in input voltage range enc + to gnd l 0 3.6 v r in input resistance see figure 11 30 k c in input capacitance (note 8) 3.5 pf digital inputs ( cs, sdi, sck in serial or parallel programming mode. sdo in parallel programming mode) v ih high level input voltage v dd =1.8v l 1.3 v v il low level input voltage v dd =1.8v l 0.6 v i in input current v in = 0v to 3.6v l C10 10 a c in input capacitance (note 8) 3 pf sdo output (serial programming mode. open-drain output. requires 2k pull-up resistor if sdo is used) r ol logic low output resistance to gnd v dd =1.8v, sdo = 0v 200 i oh logic high output leakage current sdo = 0v to 3.6v l C10 10 a c out output capacitance (note 8) 3 pf digital data outputs v od differential output voltage 100 differential load, 3.5ma mode 100 differential load, 1.75ma mode l l 247 125 350 175 454 250 mv mv v os common mode output voltage 100 differential load, 3.5ma mode 100 differential load, 1.75ma mode l l 1.125 1.125 1.250 1.250 1.375 1.375 v v r term on-chip termination resistance termination enabled, ov dd = 1.8v 100 power requirements the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 9) symbol parameter conditions ltc2195 ltc2194 ltc2193 units min typ max min typ max min typ max v dd analog supply voltage (note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v ov dd output supply voltage (note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v i vdd analog supply current sine wave input l 224 248 185 205 123 138 ma i ovdd digital supply current 2-lane mode, 1.75ma mode 2-lane mode, 3.5ma mode 4-lane mode, 1.75ma mode 4-lane mode, 3.5ma mode l l l l 16 27 23 42 20 32 27 49 15 27 23 42 19 32 27 49 15 26 22 41 19 31 26 48 ma ma ma ma p diss power dissipation 2-lane mode, 1.75ma mode 2-lane mode, 3.5ma mode 4-lane mode, 1.75ma mode 4-lane mode, 3.5ma mode l l l l 432 452 445 479 482 504 495 535 360 382 375 409 403 427 418 457 249 269 261 295 283 304 295 335 mw mw mw mw p sleep sleep mode power 1 1 1 mw p nap nap mode power 50 50 50 mw p diffclk power increase with diffential encode mode enabled (no increase for sleep mode) 20 20 20 mw ltc2195 ltc2194/ltc2193 6 219543f timing characteristics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 5) symbol parameter conditions ltc2195 ltc2194 ltc2193 units min typ max min typ max min typ max f s sampling frequency (notes 10, 11) l 5 125 5 105 5 80 mhz t encl enc low time (note 8) duty cycle stabilizer off duty cycle stabilizer on l l 3.8 2 4 4 100 100 4.52 2 4.76 4.76 100 100 5.93 2 6.25 6.25 100 100 ns ns t ench enc high time (note 8) duty cycle stabilizer off duty cycle stabilizer on l l 3.8 2 4 4 100 100 4.52 2 4.76 4.76 100 100 5.93 2 6.25 6.25 100 100 ns ns t ap sample-and-hold acquistion delay time 0 0 0 ns symbol parameter conditions min typ max units digital data outputs (r term = 100 differential, c l = 2pf to gnd on each output) t ser serial data bit period 4-lane output mode 2-lane output mode 1-lane output mode 1/(4 ? f s ) 1/(8 ? f s ) 1/(16 ? f s ) sec t frame fr to dco delay (note 8) l 0.35 ? t ser 0.5 ? t ser 0.65 ? t ser sec t data data to dco delay (note 8) l 0.35 ? t ser 0.5 ? t ser 0.65 ? t ser sec t pd propagation delay (note 8) l 0.7n + 2 ? t ser 1.1n + 2 ? t ser 1.5n + 2 ? t ser sec t r output rise time data, dco, fr, 20% to 80% 0.17 ns t f output fall time data, dco, fr, 20% to 80% 0.17 ns dco cycle-cycle jitter t ser = 1ns 60 ps p-p pipeline latency 7 cycles spi port timing (note 8) t sck sck period write mode readback mode, c sdo = 20pf, r pullup = 2k l l 40 250 ns ns t s cs -to-clk setup time l 5 ns t h sck-to-cs setup time l 5 ns t ds sdi setup time l 5 ns t dh sdi hold time l 5 ns t do sck falling to sdo valid readback mode, c sdo = 20pf, r pullup = 2k l 125 ns note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd with gnd and ognd shorted (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: when these pin voltages are taken below gnd they will be clamped by internal diodes. when these pin voltages are taken above v dd they will not be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd without latchup. note 5: v dd = ov dd = 1.8v, f sample = 125mhz (ltc2195), 105mhz (ltc2194), or 80mhz (ltc2193), 2-lane output mode, differential enc + /enc C = 2v p-p sine wave, input range = 2v p-p with differential drive, unless otherwise noted. note 6: integral nonlinearity is defned as the deviation of a code from a best ft straight line to the transfer curve. the deviation is measured from the center of the quantization band. note 7: offset error is the offset voltage measured from C0.5lsb when the output code fickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 in 2s complement output mode. note 8: guaranteed by design, not subject to test. note 9: v dd = ov dd =1.8v, f sample = 125mhz (ltc2195), 105mhz (ltc2194), or 80mhz (ltc2193), 2-lane output mode, enc + = single - ended 1.8v square wave, enc C = 0v, input range = 2v p-p with differential drive, unless otherwise noted. the supply current and power dissipation specifcations are totals for the entire ic, not per channel. note 10: recommended operating conditions. note 11: the maximum sampling frequency depends on the speed grade of the part and also which serialization mode is used. the maximum serial data rate is 1000mbps, so t ser must be greater than or equal to 1ns. 7 219543f ltc2195 ltc2194/ltc2193 timing diagrams 4-lane output mode analog input enc ? n t ench t ap n+1 enc + dco ? fr ? out#a ? d15 d13 d11 d9 d15 d13 d11 d9 d15 out#a + out#b ? d14 d12 d10 d8 d14 d12 d10 d8 d14 out#b + out#c ? d7 d5 d3 d1 d7 d5 d3 d1 d7 out#c + out#d ? d6 d4 d2 d0 d6 d4 d2 d0 d6 out#d + sample n?7 sample n?6 sample n?5 219543 td01 dco + fr + t pd t encl t data t frame t ser t ser t ser 2-lane output mode d7 d5 d3 d1 d15 d13 d11 d9 d7 d5 d3 d1 d15 d13 d11 d6 d4 d2 d0 d14 d12 d10 d8 d6 d4 d2 d0 d14 d12 d10 analog input enc ? n t ench t ap n+1 enc + dco ? fr + out#a ? out#a + out#b ? out#b + dco + fr ? t encl t ser t ser t data t frame t pd t ser sample n?5 219543 td02 sample n?6 sample n?7 out#c + , out#c ? , out#d + , out#d ? are disabled ltc2195 ltc2194/ltc2193 8 219543f timing diagrams 1-lane output mode d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 n+1 n d15 d14 d13 d12 analog input enc ? t ench t ap enc + dco ? fr + out#a ? out#a + dco + fr ? t encl t frame t data t ser t ser t pd t ser sample n?7 sample n?6 sample n?5 219543 td03 out#b + , out#b ? , out#c + , out#c ? , out#d + , out#d ? are disabled a6 t s t ds a5 a4 a3 a2 a1 a0 xx d7 d6 d5 d4 d3 d2 d1 d0 xx xx xx xx xx xx xx cs sck sdi r/w sdo high impedance spi port timing (readback mode) spi port timing (write mode) t dh t do t sck t h a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 219543 td04 cs sck sdi r/w sdo high impedance 9 219543f ltc2195 ltc2194/ltc2193 typical performance characteristics ltc2195: 64k point fft, f in = 30mhz, C1dbfs, 125msps ltc2195: 64k point fft, f in = 70mhz, C1dbfs, 125msps ltc2195: 64k point fft, f in = 140mhz, C1dbfs, 125msps ltc2195: 64k point 2-tone fft, f in = 69mhz, 70mhz, C7dbfs, 125msps ltc2195: shorted input histogram ltc2195: snr vs input frequency, C1dbfs, 125msps, 2v range ltc2195: integral nonlinearity (inl) ltc2195: differential nonlinearity (dnl) ltc2195: 64k point fft, f in = 5mhz, C1dbfs, 125msps output code 0 ?4.0 ?3.0 ?2.0 ?1.0 inl error (lsb) 0 1.0 4.0 3.0 2.0 16384 32768 49152 65536 219543 g01 output code ?1.0 ?0.4 ?0.2 ?0.6 ?0.8 dnl error (lsb) 0 0.4 0.2 0.6 0.8 1.0 219543 g02 0 16384 32768 49152 65536 frequency (mhz) ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 219543 g03 0 10 20 30 40 50 60 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 219543 g04 10 20 30 40 50 60 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 60 219543 g05 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 60 219543 g06 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 60 219543 g07 output code 32750 1000 0 3000 2000 count 4000 5000 10000 9000 8000 7000 6000 32756 32762 32768 32774 219543 g08 input frequency (mhz) 0 72 71 70 78 77 76 75 74 73 snr (dbfs) 50 100 150 200 250 300 219543 g09 single-ended encode differential encode ltc2195 ltc2194/ltc2193 10 219543f typical performance characteristics ltc2195: i vdd vs sample rate, 5mhz, C1dbfs sine wave input ltc2195: i ovdd vs sample rate, 5mhz, C1dbfs sine wave input ltc2195: snr vs sense, f in = 5mhz, C1dbfs ltc2195: 2nd, 3rd harmonic vs input frequency, C1dbfs, 125msps, 2v range ltc2195: sfdr vs input level, f in = 70mhz, 125msps, 2v range ltc2194: integral nonlinearity (inl) ltc2194: differential nonlinearity (dnl) ltc2194: 64k point fft, f in = 5mhz, C1dbfs, 105msps 0 50 100 150 200 250 300 input frequency (mhz) 90 85 80 75 70 65 100 95 2nd and 3rd harmonic (dbfs) 219543 g10 2nd 3rd ltc2195: 2nd, 3rd harmonic vs input frequency, C1dbfs, 125msps, 1v range 0 50 100 150 200 250 300 input frequency (mhz) 90 85 80 75 70 65 100 95 2nd and 3rd harmonic (dbfs) 219543 g11 2nd 3rd input level (dbfs) ?80 60 50 40 30 20 80 70 sfdr (dbc and dbfs) 90 100 130 120 110 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 219543 g12 dbfs dbc sample rate (msps) 0 210 220 230 100 219543 g13 200 190 25 50 75 125 180 170 160 i vdd (ma) sample rate (msps) 0 i ovdd (ma) 25 35 100 219543 g14 15 5 25 50 75 125 45 4-lane, 3.5ma 2-lane, 3.5ma 1-lane, 3.5ma 4-lane, 1.75ma 2-lane, 1.75ma 1-lane, 1.75ma sense pin (v) 0.6 71 70 72 73 78 77 76 75 74 snr (dbfs) 0.7 0.8 0.9 1.1 1.2 1.3 1 219543 g15 output code 0 ?4.0 ?3.0 ?2.0 ?1.0 inl error (lsb) 0 1.0 4.0 3.0 2.0 16384 32768 49152 65536 219543 g16 ?1.0 ?0.4 ?0.2 ?0.6 ?0.8 dnl error (lsb) 0 0.4 0.2 0.6 0.8 1.0 219543 g17 output code 0 16384 32768 49152 65536 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 219543 g18 11 219543f ltc2195 ltc2194/ltc2193 typical performance characteristics ltc2194: 64k point fft, f in = 30mhz, C1dbfs, 105msps ltc2194: 64k point fft, f in = 70mhz, C1dbfs, 105msps ltc2194: 64k point fft, f in = 140mhz, C1dbfs, 105msps ltc2194: shorted input histogram ltc2194: snr vs input frequency, C1dbfs, 105msps, 2v range ltc2194: sfdr vs input level, f in = 70mhz, 105msps, 2v range frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 219543 g19 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 219543 g20 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 219543 g21 ltc2194: 64k point 2-tone fft, f in = 69mhz, 70mhz, C7dbfs, 105msps frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 219543 g22 output code 32790 1000 0 3000 2000 count 4000 5000 10000 9000 8000 7000 6000 32796 32802 32808 32814 219543 g23 input frequency (mhz) 0 72 71 70 78 77 76 75 74 73 snr (dbfs) 50 100 150 200 250 300 219543 g24 single-ended encode differential encode ltc2194: 2nd, 3rd harmonic vs input frequency, C1dbfs, 105msps, 2v range 0 50 100 150 200 250 300 input frequency (mhz) 90 85 80 75 70 65 100 95 2nd and 3rd harmonic (dbfs) 219543 g25 2nd 3rd ltc2194: 2nd, 3rd harmonic vs input frequency, C1dbfs, 105msps, 1v range 0 50 100 150 200 250 300 input frequency (mhz) 90 85 80 75 70 65 100 95 2nd and 3rd harmonic (dbfs) 219543 g26 2nd 3rd input level (dbfs) ?80 60 50 40 30 20 80 70 sfdr (dbc and dbfs) 90 100 130 120 110 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 219543 g27 dbfs dbc ltc2195 ltc2194/ltc2193 12 219543f typical performance characteristics ltc2194: i vdd vs sample rate, 5mhz, C1dbfs sine wave input ltc2194: i ovdd vs sample rate, 5mhz, C1dbfs sine wave input ltc2194: snr vs sense, f in = 5mhz, C1dbfs ltc2193: integral nonlinearity (inl) ltc2193: differential nonlinearity (dnl) ltc2193: 64k point fft, f in = 5mhz, C1dbfs, 80msps ltc2193: 64k point fft, f in = 30mhz, C1dbfs, 80msps ltc2193: 64k point fft, f in = 70mhz, C1dbfs, 80msps ltc2193: 64k point fft, f in = 140mhz, C1dbfs, 80msps sample rate (msps) 0 i ovdd (ma) 25 35 100 219543 g29 15 5 25 50 75 45 4-lane, 3.5ma 2-lane, 3.5ma 1-lane, 3.5ma 4-lane, 1.75ma 2-lane, 1.75ma 1-lane, 1.75ma sample rate (msps) 0 130 i vdd (ma) 140 150 160 170 180 190 25 50 75 100 219543 g28 sense pin (v) 0.6 71 70 72 73 78 77 76 75 74 snr (dbfs) 0.7 0.8 0.9 1.1 1.2 1.3 1 219543 g30 output code 0 ?4.0 ?3.0 ?2.0 ?1.0 inl error (lsb) 0 1.0 4.0 3.0 2.0 16384 32768 49152 65536 219543 g31 ?1.0 ?0.4 ?0.2 ?0.6 ?0.8 dnl error (lsb) 0 0.4 0.2 0.6 0.8 1.0 219543 g32 output code 0 16384 32768 49152 65536 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 219543 g33 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 219543 g34 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 219543 g35 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 219543 g36 13 219543f ltc2195 ltc2194/ltc2193 typical performance characteristics ltc2193: 64k point, 2-tone fft, f in = 69mhz, 70mhz, C7dbfs, 80msps ltc2193: shorted input histogram ltc2193: snr vs input frequency, C1dbfs, 80msps, 2v range ltc2193: 2nd, 3rd harmonic vs input frequency, C1dbfs, 80msps, 2v range ltc2193: sfdr vs input level, f in = 70mhz, 80msps, 2v range frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 219543 g37 output code 32817 1000 0 3000 2000 count 4000 5000 10000 9000 8000 7000 6000 32823 32829 32835 32841 219543 g38 input frequency (mhz) 0 72 71 70 78 77 76 75 74 73 snr (dbfs) 50 100 150 200 250 300 219543 g39 single-ended encode differential encode 0 50 100 150 200 250 300 input frequency (mhz) 90 85 80 75 70 65 100 95 2nd and 3rd harmonic (dbfs) 219543 g40 2nd 3rd ltc2193: 2nd, 3rd harmonic vs input frequency, C1dbfs, 80msps, 1v range 0 50 100 150 200 250 300 input frequency (mhz) 90 85 80 75 70 65 100 95 2nd and 3rd harmonic (dbfs) 219543 g41 2nd 3rd input level (dbfs) ?80 60 50 40 30 20 80 70 sfdr (dbc and dbfs) 90 100 130 120 110 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 219543 g42 dbfs dbc ltc2193: i vdd vs sample rate, 5mhz, C1dbfs sine wave input sample rate (msps) 0 i vdd (ma) 100 110 80 219543 g43 90 80 20 40 60 130 120 ltc2193: i ovdd vs sample rate, 5mhz, C1dbfs sine wave input sample rate (msps) 0 i ovdd (ma) 25 35 80 219543 g44 15 5 20 40 60 45 4-lane, 3.5ma 2-lane, 3.5ma 1-lane, 3.5ma 4-lane, 1.75ma 2-lane, 1.75ma 1-lane, 1.75ma ltc2193: snr vs sense, f in = 5mhz, C1dbfs sense pin (v) 0.6 71 70 72 73 78 77 76 75 74 snr (dbfs) 0.7 0.8 0.9 1.1 1.2 1.3 1 219543 g45 ltc2195 ltc2194/ltc2193 14 219543f pin functions v cm1 (pin 1): common mode bias output, nominally equal to v dd /2. v cm1 should be used to bias the common mode of the analog inputs of channel 1. bypass to ground with a 0.1f ceramic capacitor. gnd (pins 2, 5, 13, 22, 45, 47, 49, exposed pad pin 53): adc power ground. the exposed pad must be soldered to the pcb ground. a in1 + (pin 3): channel 1 positive differential analog input. a in1 C (pin 4): channel 1 negative differential analog input. refh (pins 6, 8): adc high reference. see the reference section in the applications information for recommended bypassing circuits for refh and refl. refl (pins 7, 9): adc low reference. see the reference section in the applications information for recommended bypassing circuits for refh and refl. par/ ser (pin 10): programming mode selection pin. connect to ground to enable the serial programming mode. cs , sck, sdi, sdo become a serial interface that control the a/d operating modes. connect to v dd to enable the parallel programming mode where cs , sck, sdi, sdo become parallel logic inputs that control a reduced set of the a/d operating modes. par/ ser should be connected directly to ground or the v dd of the part and not be driven by a logic signal. a in2 + (pin 11): channel 2 positive differential analog input. a in2 C (pin 12): channel 2 negative differential analog input. v cm2 (pin 14): common mode bias output, nominally equal to v dd /2. v cm2 should be used to bias the common mode of the analog inputs of channel 2. bypass to ground with a 0.1f ceramic capacitor. v dd (pins 15, 16, 51, 52): analog power supply, 1.7v to 1.9v. bypass to ground with 0.1f ceramic capacitors. adjacent pins can share a bypass capacitor. enc + (pin 17): encode input. conversion starts on the rising edge. enc C (pin 18): encode complement input. conversion starts on the falling edge. tie to gnd for single-ended encode mode. cs (pin 19): in serial programming mode, (par/ser = 0v), cs is the serial interface chip select input. when cs is low, sck is enabled for shifting data on sdi into the mode control registers. in the parallel programming mode (par/ ser = v dd ), cs along with sck selects 1-, 2- or 4-lane output mode (see table 3). cs can be driven with 1.8v to 3.3v logic. sck (pin 20): in serial programming mode, (par/ ser = 0v), sck is the serial interface clock input. in the parallel programming mode (par/ ser = v dd ), sck along with cs selects 1-, 2- or 4-lane output mode (see table 3). sck can be driven with 1.8v to 3.3v logic. sdi (pin 21): in serial programming mode, (par/ ser = 0v), sdi is the serial interface data input. data on sdi is clocked into the mode control registers on the rising edge of sck. in the parallel programming pode (par/ ser = v dd ), sdi can be used to power down the part. sdi can be driven with 1.8v to 3.3v logic. ognd (pin 33): output driver ground. this pin must be shorted to the ground plane by a very low inductance path. use multiple vias close to the pin. ov dd (pin 34): output driver supply. bypass to ground with a 0.1f ceramic capacitor. sdo (pin 46): in serial programming mode, (par/ser = 0v), sdo is the optional serial interface data output. data on sdo is read back from the mode control regis - ters and can be latched on the falling edge of sck. sdo is an open-drain nmos output that requires an external 2k pull-up resistor to 1.8v to 3.3v. if read back from the mode control registers is not needed, the pull-up resistor is not necessary and sdo can be left unconnected. in the parallel programming mode (par/ ser = v dd ), sdo selects 3.5ma or 1.75ma lvds output currents. when used as an input, sdo can be driven with 1.8v to 3.3v logic through a 1k series resistor. 15 219543f ltc2195 ltc2194/ltc2193 v ref (pin 48): reference voltage output. bypass to ground with a 2.2f ceramic capacitor. the reference output is nominally 1.25v. sense (pin 50): reference programming pin. connecting sense to v dd selects the internal reference and a 1v input range. connecting sense to ground selects the internal reference and a 0.5v input range. an external reference between 0.625v and 1.3v applied to sense selects an input range of 0.8 ? v sense . lvds outputs the following pins are differential lvds outputs. the output current level is programmable. there is an optional internal 100 termination resistor between the pins of each lvds output pair. pin functions out2d C /out2d + , out2c C /out2c + , out2b C /out2b + , out2a C /out2a + (pins 23/24, 25/26, 27/28, 29/30): serial data outputs for channel 2. in 1-lane output mode only out2a C /out2a + are used. in 2-lane output mode only out2a C /out2a + and out2b C /out2b + are used. fr C /fr + (pins 31/32): frame start outputs. dco C /dco + (pins 35/36): data clock outputs. out1d C /out1d + , out1c C /out1c + , out1b C /out1b + , out1a C /out1a + (pins 37/38, 39/40, 41/42, 43/44): serial data outputs for channel 1. in 1-lane output mode only out1a C /out1a + are used. in 2-lane output mode only out1a C /out1a + and out1b C /out1b + are used. ltc2195 ltc2194/ltc2193 16 219543f functional block diagram diff ref amp ref buf 2.2f 0.1f 0.1f 0.1f 0.1f refh refl range select 1.25v reference refh refl v cm1 v cm2 v dd /2 sdo 219543 f01 cs s/h sense v ref 2.2f mode control registers sck par/ ser sdi 16-bit adc core ch2 analog input ch1 analog input s/h 16-bit adc core out1a out1b out1c out1d out2a out2b out2c out2d data clock out frame data serializer ognd ov dd enc ? v dd enc + 1.8v 1.8v pll figure 1. functional block diagram 17 219543f ltc2195 ltc2194/ltc2193 applications information converter operation the ltc2195/ltc2194/ltc2193 are low power, 2-channel, 16-bit, 125/105/80msps a/d converters that are powered by a single 1.8v supply. the analog inputs should be driven differentially. the encode input can be driven differentially or single ended for lower power consumption. to minimize the number of data lines the digital outputs are serial lvds. each channel outputs two bits at a time (2-lane mode) or four bits at a time (4 - lane mode). at lower sampling rates there is a one bit per channel option (1-lane mode). many additional features can be chosen by programming the mode control registers through a serial spi port. analog input the analog inputs are differential cmos sample-and- hold circuits (figure 2). the inputs should be driven differentially around a common mode voltage set by the v cm1 or v cm2 output pins, which are nominally v dd /2. for the 2v input range, the inputs should swing from v cm C 0.5v to v cm + 0.5v. there should be 180 phase difference between the inputs. the two channels are simultaneously sampled by a shared encode circuit (figure 2). c sample 5pf r on 15 r on 15 v dd v dd ltc2195 a in + 219543 f02 c sample 5pf v dd a in ? enc ? enc + 1.2v 10k 1.2v 10k c parasitic 1.8pf c parasitic 1.8pf 10 10 figure 2. equivalent input circuit. only one of two analog channels is shown single-ended input for applications less sensitive to harmonic distortion, the a in + input can be driven singled ended with a 1v p-p signal centered around v cm . the a in C input should be connected to v cm and the v cm bypass capacitor should be increased to 2.2f. with a singled-ended input the harmonic distortion and inl will degrade, but the noise and dnl will remain unchanged. input drive circuits input filtering if possible, there should be an rc lowpass flter right at the analog inputs. this lowpass flter isolates the drive circuitry from the a/d sample-and-hold switching, and also limits wideband noise from the drive circuitry. figure 3 shows an example of an input rc flter. the rc component values should be chosen based on the applications input frequency. transformer coupled circuits figure 3 shows the analog input being driven by an rf transformer with a center-tapped secondary. the center ltc2195 ltc2194/ltc2193 18 219543f applications information 25 25 25 25 50 0.1f a in + a in ? 12pf 0.1f v cm ltc2195 analog input 0.1f t1 1:1 t1: ma/com mabaes0060 resistors, capacitors are 0402 package size 219543 f03 figure 3. analog input circuit using a transformer. recommended for input frequencies from 5mhz to 70mhz 25 25 50 12 12 0.1f a in + a in ? 8.2pf 0.1f v cm analog input 0.1f 0.1f t1 t2 t1: ma/com maba-007159-000000 t2: coilcraft wbc1-1tl resistors, capacitors are 0402 package size 219543 f04 ltc2195 figure 4. recommended front-end circuit for input frequencies from 5mhz to 150mhz 25 25 50 0.1f a in + a in ? 1.8pf 0.1f v cm analog input 0.1f 0.1f t1 t2 t1: ma/com maba-007159-000000 t2: coilcraft wbc1-1tl resistors, capacitors are 0402 package size 219543 f05 ltc2195 figure 5. recommended front-end circuit for input frequencies from 150mhz to 250mhz 25 25 50 0.1f 4.7nh 4.7nh a in + a in ? 0.1f v cm analog input 0.1f 0.1f t1 t1: ma/com etc1-1-13 resistors, capacitors are 0402 package size 219543 f06 ltc2195 figure 6. recommended front-end circuit for input frequencies above 250mhz 25 25 200 200 0.1f a in + a in ? 0.1f 12pf 12pf v cm ltc2195 219543 f07 ? + analog input high speed differential amplifier 0.1f figure 7. front-end circuit using a high speed differential amplifer tap is biased with v cm , setting the a/d input at its optimal dc level. at higher input frequencies a transmission line balun transformer (figures 4 to 6) has better balance, resulting in lower a/d distortion. amplifer circuits figure 7 shows the analog input being driven by a high speed differential amplifer. the output of the amplifer is ac coupled to the a/d so the amplifers output common mode voltage can be optimally set to minimize distortion. at very high frequencies an rf gain block will often have lower distortion than a differential amplifer. if the gain block is single ended, then a transformer circuit (figures 4 to 6) should convert the signal to differential before driv - ing the a/d. 19 219543f ltc2195 ltc2194/ltc2193 applications information reference the ltc2195/ltc2194/ltc2193 have an internal 1.25v voltage reference. for a 2v input range using the internal reference, connect sense to v dd . for a 1v input range using the internal reference, connect sense to ground. for a 2v input range with an external reference, apply a 1.25v reference voltage to sense (figure 9). the input range can be adjusted by applying a voltage to sense that is between 0.625v and 1.30v. the input range will then be 1.6 ? v sense . the v ref , refh and refl pins should be bypassed as shown in figure 8. a low inductance 2.2f interdigitated capacitor is recommended for the bypass between refh and refl. this type of capacitor is available at a low cost from multiple suppliers. at sample rates below 110msps an interdigitated capaci - tor is not necessary for good performance and c1 can be replaced by a standard 2.2f capacitor between refh and refl. the capacitors should be as close to the pins as possible (not on the back side of the circuit board). figure 8c and 8d show the recommended circuit board layout for the refh/refl bypass capacitors. note that in figure 8c, every pin of the interdigitated capacitor (c1) is connected since the pins are not internally connected in some vendors capacitors. in figure 8d the refh and refl pins are connected by short jumpers in an internal layer. to minimize the inductance of these jumpers they can be placed in a small hole in the gnd plane on the second board layer. figure 8a. reference circuit sense 1.25v external reference 2.2f 1f v ref 219543 f09 ltc2195 figure 9. using an external 1.25v reference v ref refh refh sense c1 tie to v dd for 2v range; tie to gnd for 1v range; range = 1.6 ? v sense for 0.625v < v sense < 1.300v 1.25v refl refl internal adc high reference buffer 219543 f08a ltc2 195 5 0.8x diff amp internal adc low reference c1: 2.2f low inductance interdigitated capacitor tdk clle1ax7s0g225m murata lla219c70g225m avx w2l14z225m or equivalent 1.25v bandgap reference 0.625v range detect and control 2.2f c2 0.1f c3 0.1f + + ? ? ? ? + + refh refh refl refl 219543 f08b ltc2 195 capacitors are 0402 package size c3 0.1f c1 2.2f c2 0.1f figure 8b. alternative refh/refl bypass circuit figure 8c. recommended layout for the refh/refl bypass circuit in figure 8a figure 8d. recommended layout for the refh/refl bypass circuit in figure 8b 219543 f08c 219543 f08d ltc2195 ltc2194/ltc2193 20 219543f encode input the signal quality of the encode inputs strongly affects the a/d noise performance. the encode inputs should be treated as analog signalsdo not route them next to digital traces on the circuit board. there are two modes of operation for the encode inputs: the differential encode mode (figure 10), and the single-ended encode mode (figure 11). the differential encode mode is recommended for sinu - soidal, pecl, or lvds encode inputs (figures 12, 13). the encode inputs are internally biased to 1.2v through 10k equivalent resistance. the encode inputs can be taken above v dd (up to 3.6v), and the common mode range is from 1.1v to 1.6v. in the differential encode mode, enc C should stay at least 200mv above ground to avoid falsely triggering the single-ended encode mode. for good jitter performance enc + should have fast rise and fall times. the single-ended encode mode should be used with cmos encode inputs. to select this mode, enc C is con- nected to ground and enc + is driven with a square wave applications information encode input. enc + can be taken above v dd (up to 3.6v) so 1.8v to 3.3v cmos logic levels can be used. the enc + threshold is 0.9v. for good jitter performance enc + should have fast rise and fall times. if the encode signal is turned off or drops below approximately 500khz, the a/d enters nap mode. figure 12. sinusoidal encode drive enc + enc ? pecl or lvds clock 0.1f 0.1f 219543 f13 ltc2195 figure 13. pecl or lvds encode drive 50 100 0.1f 0.1f t1 t1 = ma/com etc1-1-13 resistors and capacitors are 0402 package size 50 ltc2195 219543 f12 enc ? enc + 0.1f v dd ltc2195 219543 f10 enc ? enc + 15k v dd differential comparator 30k figure 10. equivalent encode input circuit for differential encode mode 30k enc + enc ? 219543 f11 0v 1.8v to 3.3v ltc2195 cmos logic buffer figure 11. equivalent encode input circuit for single-ended encode mode clock pll and duty cycle stabilizer the encode clock is multiplied by an internal phase-locked loop (pll) to generate the serial digital output data. if the encode signal changes frequency or is turned off, the pll requires 25s to lock onto the input clock. a clock duty cycle stabilizer circuit allows the duty cycle of the applied encode signal to vary from 30% to 70%. in the serial programming mode it is possible to disable the duty cycle stabilizer, but this is not recommended. in the parallel programming mode the duty cycle stabilizer is always enabled. 21 219543f ltc2195 ltc2194/ltc2193 applications information digital outputs the digital outputs of the ltc2195/ltc2194/ltc2193 are serialized lvds signals. each channel outputs two bits at a time (2-lane mode) or four bits at a time (4-lane mode). at lower sampling rates there is a one bit per channel op - tion (1-lane mode). please refer to the timing diagrams for details. in 4-lane mode the clock duty cycle stabilizer must be enabled. the output data should be latched on the rising and falling edges of the data clock out (dco). a data frame output (fr) can be used to determine when the data from a new conversion result begins. the maximum serial data rate for the data outputs is 1gbps, so the maximum sample rate of the adc will depend on the serialization mode as well as the speed grade of the adc (see table 1). the minimum sample rate for all se - rialization modes is 5msps. by default the outputs are standard lvds levels: 3.5ma output current and a 1.25v output common mode volt - age. an external 100 differential termination resistor is required for each lvds output pair. the termination resistors should be located as close as possible to the lvds receiver. the outputs are powered by ovdd and ognd which are isolated from the a/d core power and ground. table 1. maximum sampling frequency for all serialization modes. note that these limits are for the ltc2195. the sampling frequency for the slower speed grades cannot exceed 105mhz (ltc2194) or 80mhz (ltc2193). serialization mode maximum sampling frequency, f s (mhz) dco frequency fr frequency serial data rate 4-lane 125 2 ? f s f s 4 ? f s 2-lane 125 4 ? f s f s 8 ? f s 1-lane 62.5 8 ? f s f s 16 ? f s programmable lvds output current in lvds mode, the default output driver current is 3.5ma. this current can be adjusted by control register a2 in the serial programming mode. available current levels are 1.75ma, 2.1ma, 2.5ma, 3ma, 3.5ma, 4ma and 4.5ma. in the parallel programming mode the sdo pin can select either 3.5ma or 1.75ma. optional lvds driver internal termination in most cases using just an external 100 termination resistor will give excellent lvds signal integrity. in addi - tion, an optional internal 100 termination resistor can be enabled by serially programming mode control register a2. the internal termination helps absorb any refections caused by imperfect termination at the receiver. when the internal termination is enabled, the output driver current is doubled to maintain the same output voltage swing. internal termination can only be selected in serial programming mode. data format table 2 shows the relationship between the analog input voltage and the digital data output bits. by default the output data format is offset binary. the 2s complement format can be selected by serially programming mode control register a1. table 2. output codes vs input voltage a in + -a in C (2v range) d15-d0 (offset binary) d15-d0 (2 s complement) >1.000000v +0.999970v +0.999939v 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1110 0111 1111 1111 1111 0111 1111 1111 1111 0111 1111 1111 1110 +0.000030v +0.000000v C0.000030v C0.000061v 1000 0000 0000 0001 1000 0000 0000 0000 0111 1111 1111 1111 0111 1111 1111 1110 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1110 C0.999939v C1.000000v 23 219543f ltc2195 ltc2194/ltc2193 applications information the frst bit of the 16-bit input word is the r/ w bit. the next seven bits are the address of the register (a6:a0). the fnal eight bits are the register data (d7:d0). if the r/w bit is low, the serial data (d7:d0) will be writ - ten to the register set by the address bits (a6:a0). if the r/w bit is high, data in the register set by the address bits (a6:a0) will be read back on the sdo pin (see the timing diagrams). during a read back command the register is not updated and data on sdi is ignored. the sdo pin is an open-drain output that pulls to ground with a 200 impedance. if register data is read back through sdo, an external 2k pull-up resistor is required. if serial data is only written and read back is not needed, table 4. serial programming mode register map (par/ ser = gnd) register a0: reset register (address 00h) d7 d6 d5 d4 d3 d2 d1 d0 reset x x x x x x x bit 7 reset software reset bit 0 = not used 1 = software reset. all mode control registers are reset to 00h. the adc is momentarily placed in sleep mode. this bit is automatically set back to zero at the end of the spi write command. the reset register is write only. data read back from the reset register will be random bits 6-0 unused, dont care bits. register a1: format and power-down register (address 01h) d7 d6 d5 d4 d3 d2 d1 d0 dcsoff rand twoscomp sleep nap_2 x x nap_1 bit 7 dcsoff clock duty cycle stabilizer bit 0 = clock duty cycle stabilizer on 1 = clock duty cycle stabilizer off. this is not recommended. bit 6 rand data output randomizer mode control bit 0 = data output randomizer mode off 1 = data output randomizer mode on bit 5 twoscomp twos complement mode control bit 0 = offset binary data format 1 = twos complement data format bits 4, 3, 0 sleep:nap_2:nap_1 sleep/nap mode control bits 000 = normal operation 0x1 = channel 1 in nap mode 01x = channel 2 in nap mode 1xx = sleep mode. both channels are disabled. note: any combination of channels can be placed in nap mode bits 1, 2 unused, dont care bits then sdo can be left foating and no pull-up resistor is needed. table 4 shows a map of the mode control registers. software reset if serial programming is used, the mode control registers should be programmed as soon as possible after the power supplies turn on and are stable. the frst serial command must be a software reset which will reset all register data bits to logic 0. to perform a software reset, bit d7 in the reset register is written with a logic 1. after the reset spi write command is complete, bit d7 is automatically set back to zero. ltc2195 ltc2194/ltc2193 24 219543f applications information register a2: output mode register (address 02h) d7 d6 d5 d4 d3 d2 d1 d0 ilvds2 ilvds1 ilvds0 termon outoff outtest outmode1 outmode0 bits 7-5 ilvds2:ilvds0 lvds output current bits 000 = 3.5ma lvds output driver current 001 = 4.0ma lvds output driver current 010 = 4.5ma lvds output driver current 011 = not used 100 = 3.0ma lvds output driver current 101 = 2.5ma lvds output driver current 110 = 2.1ma lvds output driver current 111 = 1.75ma lvds output driver current bit 4 termon lvds internal termination bit 0 = internal termination off 1 = internal termination on. lvds output driver current is 2 the current set by ilvds2:ilvds0 bit 3 outoff output disable bit 0 = digital outputs are enabled 1 = digital outputs are disabled bit 2 outtest digital output test pattern control bit 0 = digital output test pattern off 1 = digital output t est pattern on bits 1-0 outmode1:outmode0 digital output mode control bits 00 = 2-lane output mode 01 = 4-lane output mode 10 = 1-lane output mode 11 = not used register a3: test pattern msb register (address 03h) d7 d6 d5 d4 d3 d2 d1 d0 tp15 tp14 tp13 tp12 tp11 tp10 tp9 tp8 bits 7-0 tp15:tp8 test pattern data bits (msb) tp15:tp8 set the test pattern for data bit 15 (msb) through data bit 8. register a4: test pattern lsb register (address 04h) d7 d6 d5 d4 d3 d2 d1 d0 tp7 tp6 tp5 tp4 tp3 tp2 tp1 tp0 bits 7-0 tp7:tp0 test pattern data bits (lsb) tp7:tp0 set the test pattern for data bit 7 through data bit 0 (lsb). 25 219543f ltc2195 ltc2194/ltc2193 applications information grounding and bypassing the ltc2195/ltc2194/ltc2193 require a printed circuit board with a clean unbroken ground plane. a multilayer board with an internal ground plane in the frst layer be - neath the adc is recommended. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. high quality ceramic bypass capacitors should be used at the v dd , ov dd , v cm , v ref , refh and refl pins. bypass capacitors must be located as close to the pins as possible. size 0402 ceramic capacitors are recommended. the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. of particular importance is the capacitor between refh and refl. this capacitor should be on the same side of the circuit board as the a/d, and as close to the device as possible. a low inductance interdigitated capacitor is suggested for refh/refl if the sampling frequency is greater than 110msps. the analog inputs, encode signals, and digital outputs should not be routed next to each other. ground fll and grounded vias should be used as barriers to isolate these signals from each other. heat transfer most of the heat generated by the ltc2195/ltc2194/ ltc2193 is transferred from the die through the bottom- side exposed pad and package leads onto the printed circuit board. for good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the pc board. this pad should be connected to the internal ground planes by an array of vias. ltc2195 v cm1 gnd a in1 + a in1 ? gnd refh refl refh refl par/ser a in2 + a in2 ? gnd v cm2 out1c + out1c ? out1d + out1d ? dco + dco ? ov dd ognd fr + fr? out2a + out2a ? out2b + out2b ? 1 2 3 4 5 6 7 8 9 10 11 12 13 14 40 39 38 37 36 35 34 33 32 31 30 29 28 27 v dd v dd sense gnd v ref gnd sdo gnd out1a + out1a ? out1b + out1b ? 52 51 50 49 48 47 46 45 44 43 42 41 15 16 17 18 19 20 21 22 23 24 25 26 v dd v dd enc + enc ? cs sck sdi gnd out2d ? out2d + out2c ? out2c + ? + ? + ? + ? + cn1 c3 0.1f c29 0.1f c4 2.2f c2 0.1f c16 0.1f 219543 ta02 ov dd digital outputs c37 0.1f c7 0.1f c5 0.1f v dd sense sdo v dd encode input spi port par/ser a in1 + a in1 ? a in2 + a in2 ? typical applications ltc2195 ltc2194/ltc2193 26 219543f typical applications top side inner layer 3 inner layer 5 inner layer 2 inner layer 4 bottom side 27 219543f ltc2195 ltc2194/ltc2193 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description ukg package 52-lead plastic qfn (7mm 8mm) (reference ltc dwg # 05-08-1729 rev ?) 7.00 0.10 (2 sides) note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (see note 6) pin 1 notch r = 0.30 typ or 0.35 45c chamfer 0.40 0.10 5251 1 2 bottom view?exposed pad top view side view 6.50 ref (2 sides) 8.00 0.10 (2 sides) 5.50 ref (2 sides) 0.75 0.05 0.75 0.05 r = 0.115 typ r = 0.10 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 6.45 0.10 5.41 0.10 0.00 ? 0.05 (ukg52) qfn rev ? 0306 5.50 ref (2 sides) 5.41 0.05 6.45 0.05 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 6.10 0.05 7.50 0.05 6.50 ref (2 sides) 7.10 0.05 8.50 0.05 0.25 0.05 0.50 bsc package outline ltc2195 ltc2194/ltc2193 28 219543f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2011 lt 0411 ? printed in usa related parts typical application 2-tone fft, f in = 70mhz and 69mhz 16-bit adc core ch1 analog input ch2 analog input encode input s/h 16-bit adc core out1a out1b out1c out1d out2a out2b out2c out2d data clock out frame s/h data serializer pll ognd 219543 ta01a serialized lvds outputs gnd v dd ov dd 1.8v 1.8v frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 60 219543 ta01b part number description comments adcs ltc2259-14/ltc2260-14/ LTC2261-14 14-bit, 80msps/105msps/125msps 1.8v adcs, ultralow power 89mw/106mw/127mw, 73.4db snr, 85db sfdr, ddr lvds/ddr cmos/cmos outputs, 6mm w 6mm qfn-40 ltc2262-14 14-bit, 150msps 1.8v adc, ultralow power 149mw, 72.8db snr, 88db sfdr, ddr lvds/ddr cmos/cmos outputs, 6mm w 6mm qfn-40 ltc2266-14/ltc2267-14/ ltc2268-14 14-bit, 80msps/105msps/125msps 1.8v dual adcs, ultralow power 216mw/250mw/293mw, 73.4db snr, 85db sfdr, serial lvds outputs, 6mm w 6mm qfn-40 ltc2266-12/ltc2267-12/ ltc2268-12 12-bit, 80msps/105msps/125msps 1.8v vdual adcs, ultralow power 216mw/250mw/293mw, 70.5db snr, 85db sfdr, serial lvds outputs, 6mm w 6mm qfn-40 ltc2208 16-bit, 130msps 3.3v adc 1250mw, 77.7db snr, 100db sfdr, cmos/lvds outputs, 9mm w 9mm qfn-64 ltc2207/ltc2206 16-bit, 105msps/80msps 3.3v adcs 900mw/725mw, 77.9db snr, 100db sfdr, cmos outputs, 7mm w 7mm qfn-48 ltc2217/ltc2216 16-bit, 105msps/80msps 3.3v adcs 1190mw/970mw, 81.2db snr, 100db sfdr, cmos/lvds outputs, 9mm w 9mm qfn-64 rf mixers/demodulators ltc5517 40mhz to 900mhz direct conversion quadrature demodulator high iip3: 21dbm at 800mhz, integrated lo quadrature generator ltc5527 400mhz to 3.7ghz high linearity downconverting mixer 24.5dbm iip3 at 900mhz, 23.5dbm iip3 at 3.5ghz, nf = 12.5db, 50 single-ended rf and lo ports ltc5557 400mhz to 3.8ghz high linearity downconverting mixer 23.7dbm iip3 at 2.6ghz, 23.5dbm iip3 at 3.5ghz, nf = 13.2db, 3.3v supply operation, integrated transformer ltc5575 800mhz to 2.7ghz direct conversion quadrature demodulator high iip3: 28dbm at 900mhz, integrated lo quadrature generator, integrated rf and lo transformer amplifers/filters ltc6412 800mhz, 31db range, analog-controlled variable gain amplifer continuously adjustable gain control, 35dbm oip3 at 240mhz, 10db noise figure, 4mm w 4mm qfn-24 ltc6420-20 1.8ghz dual low noise, low distortion differential adc drivers for 300mhz if fixed gain 10v/v, 1nv/hz total input noise, 80ma supply current per amplifer, 3mm w 4mm qfn-20 ltc6421-20 1.3ghz dual low noise, low distortion differential adc drivers fixed gain 10v/v, 1nv/hz total input noise, 40ma supply current per amplifer, 3mm w 4mm qfn-20 ltc6605-7/ltc6605-10/ ltc6605-14 dual matched 7mhz/10mhz/14mhz filters with adc drivers dual matched 2nd order lowpass filters with differential drivers, pin-programmable gain, 6mm w 3mm dfn-22 signal chain receivers ltm9002 14-bit dual channel if/baseband receiver subsystem integrated high speed adc, passive filters and fixed gain differential amplifers |
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